An assignment algorithm with applications to integrated circuit layout
نویسندگان
چکیده
منابع مشابه
Combinatorial algorithms for integrated circuit layout
combinatorial algorithms for integrated circuit layout. Book lovers, when you need a new book to read, find the book here. Never worry not to find what you need. Is the combinatorial algorithms for integrated circuit layout your needed book now? That's true; you are really a good reader. This is a perfect book that comes from great author to share with you. The book offers the best experience a...
متن کاملAn algorithm for integrated worker assignment, mixed-model two-sided assembly line balancing and bottleneck analysis
This paper addresses a multi-objective mixed-model two-sided assembly line balancing and worker assignment with bottleneck analysis when the task times are dependent on the worker’s skill. This problem is known as NP-hard class, thus, a hybrid cyclic-hierarchical algorithm is presented for solving it. The algorithm is based on Particle Swarm Optimization (PSO) and Theory of Constraints (TOC) an...
متن کاملApplying Genetic Algorithm to Dynamic Layout Problem
In today’s economy, manufacturing plants must be able to operate efficiently and respond quickly to changes in the product mix and demand.[1] Layout design has a significant impact on manufacturing efficiency. Initially, it was treated as a static decision but due to improvements in technology, it is possible to rearrange the manufacturing facilities in different scenarios. The Plant layout...
متن کاملAn approximation algorithm for testing memories of an integrated circuit
Memory testing of an integrated circuit is a real industrial challenge, and presents several interesting original combinatorial optimization problems. A simple model for testing a set of memories, taking into account their test time and power, is first presented. Feasible solutions consist on grouping memories into lots of a maximum fixed power. The aim is to minimize the overall test time for ...
متن کاملLayout-Specific Circuit Evaluation in 3-D Integrated Circuits
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on int...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Discrete Applied Mathematics
سال: 1986
ISSN: 0166-218X
DOI: 10.1016/0166-218x(86)90064-8